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The heart of the product line is a surface mountable "base" that replaces the IC on the target board. The base accepts a PQFP package, just like a socket would, then the user can place an interface on the top of the base to connect the IC to a logic analyzer or even an emulator.

This debugging tool is ideal during an extensive debugging phase of a design, since it assures reliable and stable connection to the test equipment. This product line is also designed for high speed operation. Its compact design minimizes trace lengths and parasitic loading, allowing most systems to run at full speed without any signal degradation.

The adapter shown at right provides test points and/or interface pins to allow the user to monitor the signals on each pin of the IC. Test points are available in right angle or straight style.

*NOTE: The pad layout recommendations are for the adapters only. If users intend to solder an actual package on the target, they must consider the physical footprint of that package. Some packages have much larger footprints, where footprint is defined as "Tip to Tip dimension minus the package size", in mathematical terms:

FP = T - A as illustrated on the IC package diagram below.

The American (JEDEC) and Japanese (EIAJ) standardization comities defined the following footprints:

In other words, a package with a 3.9 mm footprint and a body size of 28 mm will have a "tip to tip" dimension (T) of 31.9 mm. The recommended X/Y dimension for that package would be a minimum of 33.9 mm.

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